This invention relates to a semiconductor memory device and, more particularly, to an random access MOS memory device of a static type performing a high speed operation with low power consumption.
In this type of semiconductor memory device, increase in the operating speed and reduction in the power consumption are required as basic important problems. However, in general, MOS transistors used in each memory cell, i.e. memory transistors, are formed in an as small size as possible for the sake of the integration density so that the load driving capacity of each memory transistor is extremely low, making it difficult to transfer the data quickly to a sense amplifier via a bit line pair. In particular, each bit line of the bit line pair has a large stray capacitance owing to a large number of memory cells being connected thereto so that the operation of sending the data in the memory elements to the sense amplifier via the bit line pair requires a very long time taking up the major part of the total time for access operation. Moreover, since each memory transistor is extremely small, the node voltages in the memory elements relative to the stored data are sensitive to voltages on the bit line pair. Therefore, it is needed to precharge the bit line pair to a certain voltage preceeding to the access operation in order to prevent the distribution of the stored data, causing a high current consumption.
Referring to FIG. 6, in a conventional semiconductor memory device, a memory cell MC11 includes CMOS type inverters 1, 2 whose input nodes and output nodes are mutually connected to each other and N-channel MOS transfer gate transistors 3, 4 having gate electrode connected to a word line 15. A pair of lines 17 and 18 are provided as a bit line pair. Although there are provided a plurality of the memory cells MC11, a plurality of the word lines 15 and a plural pairs of bit lines 17 and 18, only one set of them is shown in FIG. 6 for simplifying the explanation. That is, a memory cell MC11 as described in the above is provided at each intersection of these word lines 15 and the bit line pair 17 and 18. The bit lines 17, 18 are connected to a power supply line V.sub.D via N-channel type MOS precharge transistors 5, 6 respectively which have gate electrodes connected to a precharge control line 14. The bit lines 17, 18 are also selectively connected to data signal lines 17s, 18s via N-channel column selection gate transistors 7, 8 respectively, each of which has its gate electrode connected to a column selection signal line 23. A sense amplifier SA is provided to amplify the memory data transferred to the data lines 17s, 18s. This sense amplifier consists of a current mirror load circuit formed by P-channel type MOS transistors 11, 12 and N-channel type MOS transistors 9, 10 which have gate electrodes connected to the data lines 17s, 18s and amplify the memory data, and an N-channel type MOS transistor 13 as a current source. The read data is output from a node Nout which is a drain node of the transistor 10. The current source transistor 13 is connected to a sense amplifier control line 16 which selectively activates the sense amplifier SA. The data lines 17s, 18s are also precharged by precharge transistors 25, 26 which have gate electrodes connected to the precharge control line 14. The data lines 17s, 18s are further connected to write signal lines WBa, WBb via write gate transistors WGa, WGb respectively, the gates of these transistors being connected to a write control signal line WSW.
In this circuit, the bit lines 17, 18 and the data lines 17s, 18s are preliminary precharged to the voltage level of V.sub.D -V.sub.t, wherein the voltage V.sub.D and V.sub.t are the power source voltage of the device and the threshold voltage of the N-channel transistors 5, 6, 25, 26 respectively, according to a precharge signal PC on the precharge control line 14 during a first period. Then, in a second period, the precharge operation is completed and the sense amplifier SA is activated according to the control signal on the sense amplifier control line 16. Subsequently, the word line 15 and the column selection line 23 are selectively activated to connect the memory cell MC11 to the bit lines 17 and 18 and the data lines 17s, 18s via the column selection transistors 7, 8. Therefore, the voltage difference appears between the nodes 21, 22 in response to the data stored in the memory cell MC11. The data is amplified by the sense amplifier SA and output from the output node Nout. In this read operation, the write control signal on the control line WSW is at its low level to disconnect the data lines 17s, 18s from the write signal lines WBa, WBb.
In a write operation, on the other hand, the write control signal line WSW is changed to the high level so that the data lines 17s, 18s are connected to the write signal lines WBa, WBb, respectively, in the second period. As a result, the voltage level of one of the bit lines 17, 18 is decreased to the ground voltage VS according to write data so that the write data is written into the memory cell MC11.
FIG. 7 shows another example of conventional memory devices wherein parts equivalent to those in FIG. 6 are shown by identical symbols. This device utilizes P-channel transistors 5P, 6P, 25P, 26P as precharge means for precharging the bit lines 17, 18 and the data lines 17s, 18s up to a power supply voltage V.sub.D. This device further includes P-channel gate transistors 7P, 8P additionally to the N-channel gate transistors 7, 8. The read and write operations of this device is nearly the same as the device of FIG. 6 except for the precharge voltage and the input voltage of the sense amplifier SA. That is, in this device, the bit lines 17, 18 and the data lines 17s, 18s are precharged to the power supply voltage V.sub.D so that the input voltages of the sense amplifier SA become the voltage V.sub.D and the lower voltage. Therefore, the sense amplifier SA can operate more efficiently than in case of FIG. 6 where the input voltages at nodes 21 and 22 are V.sub.D -V.sub.t and the lower voltage.
In the device of FIG. 6, since only the N-channel type MOS transistors are used as the precharging transistors for precharging the bit and data lines, the precharge level of each line is at V.sub.D -V.sub.t, so that the voltage difference between the input nodes 21, 22 of the sense amplifier SA are comparatively low, making it difficult for the sense amplifier to sense the voltage difference quickly. In particular, when the memory device is supplied with the power voltage such as 3 V, since the threshold voltage of the N-channel transistors is usually about 1.5 V, the range of the input voltage levels of the sense amplifier is decreased to lower than 1.5 V. This voltage range markedly reduces the sensing ability of the sense amplifier to detect the potential difference on the complementary data lines and thereby increases the access time of the semiconductor memory circuit. Furthermore, when the memory device is required to operate under a lower power supply voltage such as 2.5 V, it is impossible for the sense amplifier to detect the input voltage difference.
In the device of FIG. 7, on the other hand, since the P-channel MOS transistors are used as the precharging transistors to precharge each of the bit and data lines up to the power supply voltage V.sub.D, the aforementioned problem about the inability of the sense amplifier in the device of FIG. 6 will not arise; however, one of the complementary data lines goes from the precharging level V.sub.D (power supply level) to VS (ground level) whenever a read/write operation occurs, making the power consumption of the device large. In more detail, almost all part of the power consumption in the precharging operation is the amount of the charge itself which is supplied to the bit lines 17, 18 and the data lines 17s, 18s and this amount of the charge depends on the total capacitance consisting of the stray capacitances of the bit lines 17, 18 and the data lines 17s, 18s and the precharging voltage level. Therefore, by a comparison between the circuit of FIG. 7 in which the precharge level is set to be 3 V by using the P-channel type MOS transistors as a means for precharging, and the circuit of FIG. 6 in which the precharging level is set to be 1.5 V by using the N-channel MOS transistors for precharging, the memory device of FIG. 7 consumes the precharging power which is about twice as large as that of the device of FIG. 6.
Furthermore, in the device of FIG. 7, since the precharge voltage is so high as the power supply voltage, some amount of charges from the one of complementary data lines 17, 18 will flow into the memory nodes in the memory cell MC11, so that the voltage of the low level node is raised slightly and there may occur a rewrite or destruction of the memory data in the read operation. In more detail, this voltage raise at the low level node is substantially determined as a product of the precharge voltage of the complementary data lines and the ratio of the ON-resistances of the transfer transistor 3, 4 and an N-channel transistor which is used in the inverter 1 or 2. Therefore, the higher the bit lines are precharged, the higher the voltage of the low level node is raised, making it difficult to hold the memory data correctly and the keeping holding margin of the device small.
In order to reduce the power consumption, the Japanese Patent Laid-Open Publication No. Hei 2-56799 discloses a circuit configuration in which the MOS transistors corresponding to the transistors 3, 4 in memory cell MC11 in FIG. 6 and the MOS transistors corresponding to the transistors 5, 6 for precharging the bit lines 17, 18 in FIG. 6 are replaced by P-channel type MOS transistors and the voltage source for precharging is set at the ground level. In this device, the precharge level of the bit lines corresponding to the lines 17, 18 are the voltage V.sub.t so that the input voltages of the sense amplifier become the voltage V.sub.t and a more higher voltage. Therefore the sense amplifier itself can operate more efficiently than in a case of FIG. 6 where the input voltages are V.sub.D -V.sub.t and at a lower voltage and, moreover, the power consumption of this device becomes small owing to the low precharge level. However, the driving capacity of the memory cells in semiconductor memories is very low as mentioned above and it is difficult for the memory cell to raise the voltage on the data lines quickly higher than the precharge voltage so that the high speed operation cannot be achieved in this device.
Another improvement in reduction in power consumption is disclosed in Japanese Patent Laid-Open Publication No. Hei 2-44598. In a memory device disclosed therein, the bit lines are precharged to the power supply voltage and the output signal of the sense amplifier is monitored to detect the completion of the sense amplifying operation to thereby stop activating the sense amplifier with temporarily latching the output of the sense amplifier. The word line is then deactivated and the complementary bit line pair is precharged. It becomes possible in this device to decrease the current which flows from the bit lines to the ground line via memory cells during the read operation and, additionally, cut down the current which flows in the sense amplifier even after the completion of sensing. Therefore, it is possible to reduce the power consumption of the precharging circuit during the read operation. However, in this device, since the bit lines are precharged to the power supply voltage, the voltages of the bit lines still change between the power supply voltage and the ground voltage. The reduction in power consumption is thereby restricted.